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1. The
why, where and what of low-power SoC design
Reducing on-chip power consumption has become a critical
challenge for the nanotechnology era. The traditional trade-offs
between performance and area are now being compounded by the addition
of power into the equation. Power influences designs not only in
terms of time to market, but also for cost and reliability. More...
- By Pete Bennett, Chief Consulting
Engineer for Cadence Engineering Services.
2. Focus on results in system language debate
Rather than replace existing languages or methodologies,
however, these languages promise to enhance existing development
capabilities and help coalesce them into a consistent framework
for design and verification. The combination of SystemVerilog, SystemC
and the Property Specification Language (PSL) promises a powerful
and flexible foundation for design. More...
-By Victor Berman, Group Director of Language Standards for Cadence
Design Systems.
3. Destination DSP: Methodologies
for Signal Processing Success
As FPGAs have earned greater acceptance as the platform of
choice for high-performance digital signal processing (DSP), the
design methodology gap between software DSP implementation in DSP
processors and hardware DSP implementation in FPGA or ASIC technology
has grown increasingly apparent. More...
-By Kevin Morris, FPGA and Programmable Logic Journal
4. Hear all
about it: MP3 goes surround-sound
Bit rates for encoding MP3 Surround are comparable to those
currently used to encode stereo MP3 material, resulting in files
half the size of other common compressed surround formats. More...
-By Peter Clarke,Silicon Strategies.
5. Managing
Data Flow in SoC and ReConfigurable Platform-Based Silicon Solutions
System-on-Chip (SoC) device and reconfigurable platform-based silicon
solutions combine embedded hardware and software with a staggeringly
high level of complexity. The dilemma facing design teams are only
growing, due in large part to inconsistencies of data described
within hardware and software specifications. More...
- By Steve Kompolt, Beach Solutions.
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Technology Showcase
Digital
'verification IP' is becoming more design-like
One of the first lessons of verification
IP design for reuse is modularity. And again, the reasons
are similar to those that make design IP modular. Just as
many of today's reusable virtual components are configurable
by directing the synthesis tool to include or remove modules,
the verification methodology must allow configuration of reusable
verification IP. Read
More..
-By Ron Wilson, EE Times
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eInfochips Corner
Featured
Product
SPI 3.0 Design IP
SPI 3.0 core can be used as a customized bridge solution for
Link Layer to PHY Layer devices packet based interface. The
core will be useful for people who are working on communication
system that is based on point-to-point protocol. More... |
News
eInfochips selected to operate QLogic design center
Facility in Pune, will Provide Research and Development for
Storage Area Networking ASICS, Systems and Software
More..
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Product
Announcement
Serial Attached SCSI Verification
Component
eInfochips' Serial Attached SCSI Verification Component will
be used to verify SAS designs based on SAS-1.1 specifications.
Get
in touch for more information.
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