eVCs are reusable Verification Components that can be used to establish ready-made verification environment. Each eVC is capable of acting as full verification environment or as a plug-in to an existing environment.

eInfochips' eVCs are designed for verification of today's SoC designs. With their object oriented architecture, eInfochips' eVCs are building blocks for establishing complex and comprehensive verification environment in very short time.

Description

The SONET eVC can be used for verification of any Synchronous Optical Network components like : Regenerator, Line Terminating Equipment (LTE), Section Terminating Equipment (STE), Path Terminating Equipment (PTE). It works with all HDL simulators that are supported by Specman Elite™.

Features

• Compliant to ANSI T1.105 standard
• STS-1 frame with configurable payload mapping
• Interleaved and concatenated STS-N frame generation where N = 1,3,12,48,192,768
• On-the-fly payload type mapping for the frame
• Deterministic and random payload generation for ATM and plesiochronous (DSx) traffic
• Virtual Tributary (VT) grouping for DSx as well as custom payload
• On-the-fly Transport Over Head (TOH) and Path Over Head (POH) configuration for single frame or multiple frame pattern
• Error injection in Overhead octets and Pointers
• On-the-fly pointer adjustment via New Data Flag (NDF) and justification field
• Programmable VT Pointer
• Configurable Frame scrambling engine
• AIS Protocol Checking and event generation
• Parity calculation with/without error as per configuration
• Configurable abstraction and analysis of :
  • Payloads for different mappings like ATM, DSx
  • Interleaved & Concatenated STS-N frames
  • Super frame and VT groups
  • Overhead per STS-1 frame
• Scoreboard monitoring of:
  • Payload for different mappings
  • TOH and POH
  • VT Overhead and Pointers
  • Payload Point