FIR filters are one of the most basic building blocks used in digital signal processing.

In digital signal processing the multiply accumulates must be performed at an ever-increasing rate and demands in the billions of MACs per second range are now common.

Data presented at the filter input port is stored within the filter module in an array of internal registers - one per tap.

Filter coefficients provided by the user are stored in internal look-up tables of the FPGA and accessed during filter operation in accordance with the parallel-distributed arithmetic algorithm.

Partial results from each look-up table are summed to form a final result at the filter output port.

Features

• High-performance finite impulse response (FIR)
• Supports Virtex™ and Spartan II
• Parallel Distributed Arithmetic architecture
• Input data word: 16 bits
• Coefficient data width : 24 bits
• Output data word: 24 bits
• Signed Arithmetic
• Internal cascading for better performance
• Works on both symmetrical and asymmetrical coefficients