XAUI UVC

eVCs are reusable Verification Components that can be used to establish ready-made verification environment. Each eVC is capable of acting as full verification environment or as a plug-in to an existing environment.

eInfochips' eVCs are designed for verification of today's SoC designs. With their object-oriented architecture, eInfochips' eVCs are building blocks for establishing complex and comprehensive verification environment in very short time.

Description

The XAUI eVC can be used to verify any IEEE P802.3ae/D4.0 compliant MAC or PHY device. The eVC can be used for the functional verification of IP cores and SoC designs incorporating Ethernet MAC and PHY devices with XGXS layer functionality. It can be configured to have an unlimited number of Ethernet ports, each interfacing with one of the DUT's Ethernet ports. It works with all HDL simulators that are supported by Specman Elite. The eVC is provided with plug & play DTE and PHY XGXS modules, with XAUI interface in between, thus allowing the user to test the DUT with both - XAUI and XGMII interfaces, for both MAC and PHY.

Features

• Compliant to IEEE P802.3ae/D 4.0 Specifications
• Simulates single or multiple Ethernet devices on a medium, generating and collecting Ethernet packets
• Supports XAUI interface
• Supports configuration of different ports independently
• Users can control generation of transactions for each device model
• Monitors protocol and reports violations
• Fully configurable error generation allows testing of error detection mechanisms under realistic scenarios
• Utilizes 'plug & play' eVC methodology to ensure full compatibility and inter-operability with other eVCs
• Supports the management interface for XAUI protocol
• Verifies MAC or PHY DUT with XAUI