New technologies are redefining the way people communicate. Edge, Access and Core devices are changing to adapt themselves to faster modes of transport, demands for intelligent routing of information, multi-services and "anywhere anytime" access.
We have the expertise of working across numerous projects ranging from devices used in Broadband Infrastructure, IP Networks, Wireless Communications and Convergence.
Our Services Include
- Pre & Post Networking chip Design, Verification, Validation, BSP & Drivers Testing, Application Testing and System Testing
- Wireless Expertise in PAN, LAN, and WAN
- MAC implementation in DSPs / FPGAs and PLDs
- UWB SoC Prototyping, 802.11x Integration, Drivers/GUI Development/Testing
- SDR (Software Defined Radio) validation to bring-up to GUI/API development
- Networking Tools
- IXIA:
- IxANVL (Protocol Conformance Test Suite)
- IxChariot (Performance, Stress Test Suite)
- OC48/OC192 line rate TGA (Full featured protocol conformance, stress andperformance suite)
- IxNetwork, IxRouter
- Adtech:
- Automation Tools
- Scripts:
- Tcl/Tk, Perl / Shell, Python/Silk,
- Vendor Tools:
- Mercury Test Director, WinRunner, xRunner, QTP
- Protocol Analyzer: Finisar, Ethereal
- Certification: Sparta, Microsoft HCT, WLK
- Benchmarking Tools: iperf, netperf, ntttcp, MVAPICH2, IOMeter, IOZone
- Test Automation framework including Layer 2 & Layer 3
| ATM SAR |
Solution With eXpress DSP compliance - for TI's C64xx processor family. more... |
| KVM/IP |
Complete product solution consisting of DSPs and Video ADC on the board for transporting KVM signals over IP. more... |
| OC-48 Framer / Mapper Verification |
Verification environment development and validation of a high-density, combination OC-48 framer, multichannel HDLC communication controller and ATM cell delineator ASIC of 35 million gate density. more...
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| Network Co-processor SoC |
Verification of the blocks of Network Co-processor SoC covering BFM implementation, complete system-level co-verification and Regression Suite development within a scheduled time frame. more...
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| Packet Express (ATM SAR and Traffic Manager) |
Design and in-depth verification of ATM SAR - The design consisted of Utopia interface and customized processor interface to data exchanges to other chips and software. The chip works at 133 MHz with 64 bits data bus width. more...
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| Verification of OC-192 line card framer chip |
-SONET/SDH/OTN framer/mapper chip with virtual concatenation to contiguous concatenation conversion and reverse support -Verification environment development for functional verification at block level and mini chip level - Using SONET eVC, UPI eVC, Scoreboard eVC in environment - Tools: Specman, Modelsim. more...
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| Cell library conversion |
The library to be converted consisted of custom cells, made up by using 0.25 um technology. The cells were of varying types consisting from the simple "via chains" to "diodes", "resistors", "capacitors", "pnp junctions" and "FET based" to complex "memory cells" and "ring oscillators". more...
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| Verification of networking SoC |
We served High Sigma (Zero Defect) quality SoC verification services for a chip-set, multi-million gate VLSI devices targeted for storage area networking (SAN) needs. With multiple Giga-bits/second throughput, the SoC delivers scalability, portability and comprehensive solutions as per the need more...
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