Internet telephony SoC for next generation networks help enable carrier-grade Voice over Packet (VoP) network equipment with higher channel density, greater flexibility, higher reliability and lower power than existing solutions. This helps service providers deploy, provision and manage a greater range of customized products and services.

Our client was a California (USA) based company providing silicon for enabling the highest density voice-over-packet systems supporting millions of channels across the full range of voice processing applications and packet based networks.

eInfochips’ Role:

eInfochips’ role was to perform functional verification of a 17 Million gates Internet telephony manager SoC which included DRAM, SDRAM, PCI, DMA, DSP, RISC processor interface and physical verification on a board containing tape out Silicon sample, within a short duration.

• Defining the complete test plan, test-benches design and implementation for RTL stage
• Test-vector generation, regression scripts implementation and regression suite maintenance for RTL
• Defining complete test plan for board level Silicon verification
• Verification of functionality on chip compliant to RTL level functionality
• Test-vector generation covering board level diagnosis, CPLD code interface and API directed vectors & regression testing on Silicon

How was this achieved?

• Defining the complete test plans and test benches for the SRAM, SDRAM interfaces
• Generating the test vectors for the modules to verify them at the module as well as full chip level
• Implementation of JTAG, test-vector generation, and regression scripts creation
• Writing Application Programs to program various system interfaces for the various combinations
• Generated directed test vectors through automatic utilities written in scripting language
• Verified individual instructions of the processor, random interrupts, program memory and data memory, which involves RISC and PACKET instruction test-vector generation
• Covered performance analysis by writing Protocol checkers and monitors. Improved line coverage, conditional coverage of core by code coverage tools
• Simulated the blocks on hardware accelerator in order to increase the simulation time
• Defined a complete test plan for post-fabrication silicon verification of the chip and implementation of the same, by writing the test-vectors for the chip using software APIs
• Defined the complete test plans and test benches for the board level testing of taped out silicon. Executed test vectors on chip bring up level which were fired on RTL
• Initial verification commenced with the board at 4MHz and finally achieved the board working at 66MHz with Silicon
• Written application programs to configure various system interface
• Coherent synchronization between verification team, lab team and design-RTL team
• Executed 2200 directed test cases with 100% coverage on 17 Million gates ASIC
• Development of randomizer of different modules for the chip level bring up testing
• Core will be working on board at 100MHz as final silicon verificatio