Sr. Physical Design Engineer

Required Skills:

• 3-5 years of extensive experience in large VLSI physical design implementation on 0.18u or below technology.
• Must have hands on experience of chip tapeouts including Physical Verification, Decks (DRC/LVS/ERC/Antenna) & Tape out.
• Must have solid experience on Magma/Cadence/Synopsys tool suite (P&R, physical extraction and verification, timing verification, etc.)
• Some experience with synthesis, timing analysis and DFT is desired.
• Experience with Calibre and Spice is a plus
• Backend ASIC Design
• Good good verbal/written communication, need to be self-motivated, need to take full ownership of the task.
• B.E./B.Tech., M.E./M.Tech./M.S. preferable

Job description

• As a Senior Physical Design Engineer, you will be working on full chip integration and the timing & physical aspect of multi-million gate ASICs. This includes floor-planning, generating timing constraints, generating timing models for custom blocks, performing timing driven P&R, static timing analysis, deriving timing closure using various strategies e.g. buffer resizing, repeater insertion, etc., performing clock tree insertion and clock skew analysis, creating power distribution scheme, analyzing IR-drop, signal integrity of the whole chip.