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ASIC Physical Design

ASIC Physical Design Expertise:

eInfochips’ extensive and innovative Physical Design services flow is designed to meet the demands of today's deep sub-micron ASIC designs.Our operational excellence helps to achieve less than 3 iterations for DRC/LVS clean GDSII.

eInfochips’ back-end design expertise includes custom layout of IOs and Analog macros, layout creation for leaf cells and top level integration, layout verification through LVS, DRC & DFM checks, RV/IR/EM fixes, reliability checks and executing Engineering Change Orders (ECO). Our team is proficient at LVS/DRC debug, custom design tools like Cadence Virtuoso, DFM/RV/IR/EM concepts and scripting skills.
eInfochips' experienced engineering team can help you build successive iterations of a design to address a specific customer requirement at low turnaround time and resource utilization. Our engineers by virtue of their design and verification expertise and experience throughout the physical design flow can ensure that your tape-out is successful.

eInfochips specializes in Synopsys, Magma & Cadence design tools for place and route and has proven ASIC Mask design capabilities with expertise in tools offering Design Rule check and Antenna check.

Success Stories:

  • RTL to GDSII for a Networking chip:
    Services offered include physical layout, post layout, DRC LVS and formal verification using Mentor & Magma tools on 0.09um chartered semiconductor with 9 layers.
 

Physical Design Services

  • Standard cell based ASIC/SoC implementation
    • RTL Synthesis
    • DFT, ATPG & Fault grading services
    • Hierarchical Floor planning and Partitioning
    • Multi-power island designs, power analysis (low power design)
    • Place & Route
    • Customized Clock Tree Synthesis
    • Signal Integrity Analysis
    • ECO Implementation for functional and timing fixes
  • Custom mask design for schematic driven digital/analog design
  • Mask layout for semi custom standard cell library for automatic or schematic driven datapath/control design
  • Signoff Services - Power, EM, IR Drop, Noise, STA with On-Chip Variation (OCV) and Multi Mode Multi Corner (MMMC),ATPG, Layout Verification, Formal verification
  • Physical Verification & DFM
  • Post-Layout ATPG Simulation
  • Chip / ASIC Layout Migration

ASIC Physical Design Processes
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Differentiators

  • Global customer exposure (US, Europe, Japan, India) allows us to understand each customer ‘s unique requirements
  • Expertise in technologies ranging from 45nm to 180nm with different processes
  • Experience in tape-outs to foundries like TSMC, CHARTERED, UMC, TI & TOSHIBA
  • Designs implemented with IP modules such as PLL, SERDES, ADC, DAC, DLL
  • Successful tape outs / polygon generations for
    • Low power designs
    • High speed interface designs
    • Hierarchical designs
    • Flip chip designs
    • Multi-clock domain designs
  • Engineering team capable of handling large SoCs all the way to GDSII generation with DRC/LVS/ANTENNA clean-ups on industry standard sign off tools
  • Ability to rapidly scale team size via training and processes

Tools Expertise

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