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DDR2 SDRAM SystemVerilog Memory Model Generator Tool

Reduce your verification time and maximize the memory verification coverage through eInfochips’ DDR2 SDRAM SystemVerilog based Memory Model Generator Tool.

eInfochips’ DDR2 SDRAM Model Generator is a GUI (Graphical User Interface) based integrated memory generation tool that allows you to configure parameters of DDR2 SDRAM memory (covering all leading memory vendors) and generates a SystemVerilog behavioral model.

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Parameters like memory size, data width, clock rate, cycle time, CAS latency and data rate can be configured using this tool.
DDR2 SDRAM Model Generator comes in 2 modes:

  • Typical Mode – User may choose the memory vendor (Micron®, Samsung®, Hynix® & Elpida®) and part number within a huge database
  • Custom Mode – User may create customized DDR2 SDRAM behavioral model from scratch by configuring every parameter of DDR2 SDRAM through the configuration selection algorithm (CSA)

Currently the tool supports DDR2. Please write to us at This e-mail address is being protected from spambots. You need JavaScript enabled to view it if you need models for DDR, DDR3, NAND Flash, NOR Flash, QDR or XDR.

Tool Features

  • Supports DDR2 memory from Micron®, Samsung®, Hynix® & Elpida®
    • Large library of part numbers for each supported memory vendor
    • Allows to generate customized memory models
    • Covers all available memory parts in a single solution
  • Reduces the verification efforts and enhances verification coverage
  • Low-cost HVL based solution with ease of use and ease of integration
  • TCL/TK based GUI, no special system specifications required

Features of generated Behavioral Model

  • Independent entities that can be plugged into the verification environment
  • Fully compliant to JEDEC standard JESD79 – 2D
  • Built-in coverage (integrated coverage)
  • Option to
    • turn on/off initialization
    • enable/disable DDR2 interface checkers
    • enable/disable coverage

DDR2 SDRAM SystemVerilog Memory Model Generator Tool

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Why choose eInfochips’ DDR2 SDRAM SystemVerilog Model?

Limitations of available Memory Models eInfochips’ Memory Model Value Proposition
Available only in Verilog and VHDL SystemVerilog memory model
No randomization Randomized configuration per simulation
Encrypted / protected model Single model for all configurations
Limited support from memory vendor for simulation model Support available
Each model simulated to fixed configuration Model can be constraint to support one (or more) particular vendor; model can be constraint for a specific (or list) part number
Limited support for configuration (Min. and Max value) Wizard based configuration support
Need to maintain different files for each mode for each vendor Single file to maintain (instead of 1 per vendor per part)
Limited error scenario support Enhanced error scenario support
Model design and log output varies from vendor to vendor Common logging/reporting mechanism

Deliverables

Deliverables include completely verified SystemVerilog DDR2 SDRAM generator encrypted code, user guide and release notes.

Micron®, Samsung®, Hynix® & Elpida® are trademarks of Micron Technology, Samsung, Hynix Semiconductor Inc. and Elpida Memory Inc respectively. Other names and brands may be claimed as the property of others

Product images shown above are for representation purposes only.

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