RTL to GDSII Implementation of a 90nm Networking Chip

Executive Summary

Our customer is a privately held semiconductor company based in North America.

The chip has a multi-clock domain and a high speed interface application used for networking purposes. The design contains various blocks, namely Memory controller, Configuration controller, Dual port RAM, Ring oscillator, Fuse, Programmable logic loop, MAC PCS control and MAC PCS LITE control block.

The customer wanted to develop a networking chip that offers ASIC-like performance and logic efficiency, while still maintaining an FPGA-like flexibility. Being a small sized company with tighter budgetary requirements, the customer decided to outsource physical design of the chip to eInfochips for achieving "first time right silicon".

eInfochips delivered a clean DRC/LVS netlist using an in-house three stage design methodology. Our team successfully performed physical layout, post layout, DRC / LVS and formal verification of the networking chip using industry standard tools on 90nm technology nodes.

The Customer

Our customer develops next generation configurable solutions for a wide range of networking-based platforms. Their ground-breaking work in building advanced processors and ASICs has allowed them to develop the insight to chart a new course for the networking, telecom, storage, and wireless base station markets. Its products include Configurable Switch Array chip that moves, stores, and edits packets; and EDA tools.

The Challenge

  • Meeting setup slack with required slew and skew targets between different clock domains
  • Floorplanning each block for macro placement, congestion, IR drop and DRC cleanup

The Solution

eInfochips' team offered the following physical design services:

  • RTL to GDSII implementation with final Netlist
  • DRC and LVS clean-ups in Magma and Calibre
  • Formal verification
  • Flow development
  • Scripting in mTCL, Perl and Make utility
  • Sign-off level timing analysis
  • DEF based post tape out flow for ECO

Technology

  • Industry: Networking
  • Technology: 90nm Chartered
  • Design Complexity: 10 Blocks with each one being more than 300K Place able Objects
  • Frequency: 1.3 GHz
  • Tools:  Magma (Blast Fusion) , Mentor (Calibre, IC Station)

The Benefit

  • eInfochips' team delivered a GDS II that operates at frequency of 1.3 GHz, within the allocated time frame,  despite dealing with multiple implementation challenges
  • eInfochips’ offshore team worked closely with customer’s engineering team and delivered DRC / LVS clean GDSII within three iterations, that allowed the customer to do early sampling of the products