Xilinx Virtex-5 FPGA based Design, Verification and Board bring-up for Automatic Tester Equipment (ATE)

Executive Summary

Our customer is a leading supplier of Automatic Test Equipments to the world’s major semiconductor, electronic, automotive companies.

The FPGA is one of the design units in tester system and resides on channel card. It is connected to several other chips on system. This design has been implemented on Xilinx Virtex-5 FPGA and has on chip PCI-Express Endpoint Block Plus hard macro from Xilinx as one of its external interfaces. Major building blocks are Instrument Sync Link, Move Link, Data bus, and Clock Control.

eInfochips’ relationship with the customer started with a pilot project as the customer was not satisfied with our competitor’s performance. Impressed with eInfcohips' process maturity, technical capability, delivery excellence, and right number of resource utilization, the customer decided to formalize its relationship with eInfochips through a dedicated offshore development center (ODC) at Ahmedabad. Soon, eInfochips started a new phase in the relationship by winning projects on the development of next generation ATE products for the customer.

eInfochips' ASIC team took up the task of analyzing the architecture having critical area and timing requirements and came up with a plan for Design, Verification, Implementation and Board bring-up of multi-million gate FPGA. The FPGA was successfully demonstrated to work at full speeds and fully complied with the performance requirements.

The Customer

Our customer is a leader in providing Assembly Test, Semiconductor Test and Vehicle Diagnostic Solutions. The customer is the world’s largest supplier of semiconductor test equipments for logic, RF, analog, power, mixed-signal, memory technologies, and SoC devices. 

The Challenge

• The challenges involved
  • Multi-clock domain design
  • Meeting timing requirements provided by board design team
  • Seamless integration with third party core for PCI Express

The Solution

eInfochips’ team took the ownership of the complete project cycle and worked on the following aspects of the FPGA development:

• Design: Developed RTL codes for customer's proprietary logic, interfaces to the customer's IPs on their system bus and transaction layer interface logic for the PCIe interface to the customer's IP
• Verification: Developed new transactors, modified legacy test environment, enhanced coverage for verification, developed test cases to achieve high coverage and performed gate level simulation of the design
• Board bring-up: Ensured that the FPGA was running perfectly on the system hardware. This was accomplished by working closely with design, verification and software teams and debugging at board level 
• Other tasks: LEDA check, CDC (Clock Domain Crossing) check, logic equivalency, timing clean FPGA synthesis and PAR.

Technology

• Industry: Semiconductor – ATE
• Device: Xilinx Virtex-5 FPGA
• Complexity: 20 Million Gates
• Languages:  Verilog (Design), C (Verification)
• Tools: Xilinx ISE 10, NCVerilog, Conformal, Encounter, LEDA, Synplify
• Platform: UNIX, LINUX

The Benefit

• Complete spectrum of services provided with quality deliverables
• Excellent co-ordination between three teams - Design, Verification, and Board bring-up enabled us to complete the project in the defined timeline
• The FPGA was successfully demonstrated to work at full speeds and fully complied with the performance requirements stated by the customer