Reed Solomon Encoder

Reed Solomon Encoder

This IP implements a Reed Solomon Encoder. The IP is compatible with many standards, which includes European DVB standard, IEEE 802.16, IntelSat Earth Station (IESS), ETS 300 421, ETS 300 429 etc.

It accepts the k blocks of data symbols and generates n blocks of code symbols as per the user defined generator polynomial and primitive polynomial.

The core is designed for efficient implementation on FPGA and ASIC.

Applications

Typical applications of this IP are:

Any communication system like Satellite Communication, Telecommunication, Video and Audio Broadcast.
Data storage systems (ex: CD-ROM, Hard Disks etc.)

Functional description

This IP implements systematic RS encoder. The RS encoder accepts k blocks of symbols and generates n blocks of code words. n-k symbols are the parity. The number of errors that can be corrected for the RS encoder with defined n and k is given by t, where 2t = n - k.
A Reed Solomon Code is distinguished by two polynomials: the primitive polynomial and generator polynomial. The data and codeword symbols are member of Galois field as defined by primitive polynomial. The parity is generated as defined by generator polynomial.
The Reed Solomon encoder accepts the data symbols and generates the code word as defined by the generator polynomial.

Features

Implements many Reed-Solomon coding standard
Executable file generates RTL code as per user defined parameters
Accepts data serially and in burst
Supports any primitive polynomial
User defined generator polynomial
Symbol width range is 3-31 bits
Code symbol range is 4-231 symbols with parity up to 999 symbols
Supports shortened RS codes
Low latency output implementation. Latency of two clocks between first data input and first data output
Simple interface allows easy integration into larger system
Executable file which can generate Verilog RTL code as per user defined parameters or Verilog RTL code for particular RS encoding specification or technology specific netlist available