OVM 1.0 Class based AMBA AXI

The AXI System Bus is an on-ship system bus that connects an embedded processor such as an ARM core to high-performance peripherals, DMA controllers, on-chip memories and interfaces. AXI is a new generation of the AMBA bus intended to address the requirement of the high performance synthesizable designs.

The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for use in high-speed SoCs.

eInfochips’ AMBA AXI Verification component (VIP) is based on OVM methodology that allows coverage driven verification suitable for verifying AXI Master, AXI Slave and the AXI bus with the various combination as the DUT.

Features

AMBA AXI VIP is a ready-made highly configurable System Verilog, OVM Class based Verification Component suitable for the verification of the AMBA AXI master & slave DUTs and AXI bus. The AXI  VIP provides all necessary building blocks to easily test master/slave/bus DUT with the AXI bus protocol. The Verification Component can be easily configured and integrated with the verification environment. The key features are as below:

  • Support for all kinds of burst transfer like FIXED, INCR and WRAP.
  • Generates different kind of response like OKAY, EXOKAY & SLVERR which can be random as well as user defined. User can inject particular response in particular transfer.
  • Checks for the AMBA AXI through interface level assertion.
  • Support for the multiple bus widths (8, 16, 32, 64, 128, 256, 512, 1024 bits).
  • Configurable timeout facility in both master and slave to generate response timeouts as per user configuration
  • Configurable AXI slave memory address space.
  • Out-of-order response handling
  • Narrow transfer support
  • Unaligned address support
  • Atomic operations support
  • Protocol checkers / SV assertion.
  • Functional Coverage.
  • Any module (Master/Monitor/Slave) can be enabled or disabled
  • Coverage and assertions can be enabled or disabled
  • Random as well as user defined packets can be generated to hit particular scenarios.
  • Multi-master and multi-slave support (if interconnect is available)
  • Error injections for masters and slave.
  • DUT can be in VERILOG or VHDL.