e80186 16 bit Processor Core

The e80186 is a 16-bit, highly integrated microprocessor that includes system components like chip select logic, DRAM refresh logic, powersave logic, and so on, on a single chip. It has four times the throughput of the comparable Intel chip.

Features

  • Available under terms of the SignOnce IP License
  • Supports Virtex™ and Virtex-II devices
  • Operation Modes:
    • Enhanced Mode
      - DRAM Refresh Control Unit
      - Power-Save Mode
      - Compatible Mode
  • Integrated Feature set
    • ClockGenerator
    • Two Independent DMA Channels
    • Programmable Interrupt Controller
    • Three Programmable 16-Bit Timers
    • Dynamic RAM Refreshing Unit
    • Programmable Memory State Generator
    • Peripheral Chip Select Logic
    • Programmable Wait
    • Power-Save Mode

Functional Description

  • The Central Processing Unit (CPU) executes instructions, which include fetching, decoding instruction, and generating appropriate requests to the BIU.
  • The Bus Interface Unit (BIU) resolves priority issues among various bus masters and generates hand shaking signals for external hardware devices.
  • The Programmable Interrupt Controller Unit (ICU) is capable of handling four external, or five on-chip and one nonmaskable requesters, with the flexibility of defining priorities and masking at individual levels (other than NMI).
  • The Direct Memory Access Controller (DMA) unit enables data transfers between memory and IO devices without requiring the CPU’s intervention. The unit can be triggered externally or internally (via a timer or software).
  • The timer’s interrupt can initiate DMA transfers.
  • The Timer/ Counter Unit (TCU) has three real-time programmable timers. Two have the capability of prescaling and can be clocked internally or externally. All timers are capable of operating in single as well as continuous count.
  • An interrupt from one of the timers can initiate DMA transfers.
  • The Refresh Control Unit (RCU) is capable of refreshing 256 bytes of Dynamic Memory Devices by generating programmable periodic dummy read cycles.
  • The Chip Select Unit (CSU) has six dedicated programmable chip-enabling signals for memory and seven conjugated (selecting 128 bytes) chip-enabling signals for I/O or memory. It is capable of programmable wait state insertions (maximum three).