45nm Graphics SoC Physical Design

Executive Summary:

Our customer is a semiconductor design innovator leading the next era of vivid digital experiences with its ground-breaking processor technology.
45nm graphic soC
The next generation 45nm Graphics chip is targeted at various applications such as gaming devices, notebooks, and high-end servers. The chip is multi clock domain design using clock gating and working on 1GHz frequency having two master clocks. It is mapped at below 45 nm TSMC library and contains 10 metal layers.
The customer wanted to lead the market by first releasing graphics core based on below 45nm node. The customer partnered with eInfochips based on proven track record of successfully managing complex RTL to GDSII implementation projects involving advanced process technology nodes and low power design techniques.
eInfochips performed physical design of various blocks of high performance graphics chip on TSMC's process technology below 45nm. eInfochips team performed IC layout and sign-off services - STA, DRC / ERC / LVS cleanup, Crosstalk, IR Drop analysis etc. while controlling power consumption, high congestion, and stringent slew limit.

The Customer:

Our customer is an American multinational semiconductor company that develops computer processors and related technologies for commercial and consumer markets. Our customer's graphics and computing technologies power a variety of solutions including PCs, game consoles and the servers that drive the Internet and businesses.
  • Dynamic IR drop issues due to higher switching
  • Controlling total power consumption due to leakage power
  • Complex low power flow using UPF 2.0 and its power grid structure
  • Several iterations to finalize the floor plan shape initially
  • Stringent slew limit of 156ps for data and 100ps for clock
  • Balanced skew less than 50ps for all 14 root clock buffers connected to top level clock meshes in Multi point CTS implementation
  • High congestion in blocks due to higher number of feed-through count
  • Implementing block with initial utilization of 70%

The Solution:

eInfochips team worked on the following aspects as part of the physical design effort:
  • Netlist to GDSII Implementation
  • Floorplan, pin placement & special low power cell insertion using Cadence Encounter
  • Place & Route, Clock tree synthesis, Routing using Synopsys ICC
  • Optimization after Placement/CTS/Routing using Sierra Pinnacle tool
  • Static and Dynamic Signoff IR Drop Analysis using Apache Red Hawk
  • Formal verification checks using Conformal LEC
  • Low power static rule checks using Synopsys MVRC
  • Signoff STA using PT
  • Signoff Crosstalk using PTSI
  • Signoff includes timing, DRC, ERC and LVS using Calibre

The Technology:

  • Industry: Computing
  • Technology: Below 45nm TSMC (10 Metal layers + RDL)
  • Design Complexity:
    • 342 Memories (Digital + Analog)
    • 2700K instances
  • Frequency: 1 GHz
  • Languages: Perl, TCL, and Make for Scripting
  • Tools: Synopsys - ICC, MVRC, PrimeTime; Cadence - SoC Encounter, Conformal LEC; Apache Red Hawk, Mentor Graphics Calibre

The Benefit:

  • Helped customer achieve time to market goal ahead of its close competitor
  • Successfully delivered GDSII on time in spite of numerous netlist releases from front end resulting into repetitive efforts in design closure